Congestion and Power Reduction by using Merged Flip Flops

Shanigarapu Nareshkumar

This paper presents Integrated circuit design process. In IC design process it has different steps like Floor plan, Power plan, Placement, Clock tree Synthesis and Routing. It must have a relation in between each and every process. Among these it has a significant relation in between clock and power consumption. The power consumption of IC can be depending on clock toggles. By replacing of few single bit Flip flops by multi-bit Flip flops it can reduces power. By merging of Flip flops it reduces congestion and area of the design. This design can reduce power by approximately 30%. Congestion plays a major role in VLSI circuits. This design optimizes congestion to the accurate level. And it meets the perfect timing. In order to meet the timing it should meet setup as well as hold.

Select Volume / Issues:

• Volume 5,Issue 6, Nov. 2014

Year:

2014

Type of Publication:

Article

Keywords:

Clock Toggle; Power consumption; Multi-bit Flip flops; Congestion

Journal:

IJECCE

Volume:

5

Number:

6

Pages:

1327-1330

Month:

November