Performance Evaluation of FPM on Spartan Family FPGAs and Analyze Its Effect on Bonded IOBs

Pardeep Sharma; Gurpreet Singh; Hartej Singh Saini

VHDL programming for IEEE single precision floating point multiplier module have been explored because floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed. Floating point operations are hard to implement on FPGAs i.e. on reconfigurable hardware’s because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. The parameter number of bonded IOBs (Input Output Blocks) has been analyzed while implementing the floating point multiplier on Spartan 2, Spartan 2E, Spartan 3 and Spartan 3E FPGA’s.

Select Volume / Issues:

• Volume 3 Issue 6, Nov. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Floating Point Multiplier; FPGAs; Memory; Xilinx and Spartan

Journal:

IJECCE

Volume:

3

Number:

6

Pages:

1532-1536

Month:

November