Implementation of 64-Bit Approximate Multiplier for Accurate and High-Level Processing

Ragini Singh; Prof. Sandip Nemade

Approximate computing has received significant attention as a promising strategy to enhance performance of multiplication. Various arithmetic operations such as multiplication addition, subtraction are important part of digital circuit to speed up the computation speed of processor. This paper presents 64 bit approximate multiplier for high speed and low delay for advance digital signal processing. Previous it is designed for 16 bit and 32 bit for various applications. Research work is focus on hardware-level approximation by introducing the partial product perforation technique and dadda multiplier for designing approximate multiplication circuits. Xilinx 14.7 is used to implementation with verilog programming language.

Select Volume / Issues:

• Volume 11,Issue 1,Jan. 2020

Year:

2020

Type of Publication:

Article

Keywords:

Approximate; Dadda; Multiplier; Verilog; Speed

Journal:

IJECCE

Volume:

11

Number:

1

Pages:

1-7

Month:

January

ISSN:

2249-071X