Study Analysis Of Various Low Power Zero Partial Product Bypass Multipliers

Rutesh S. Lonkar; Pravin P. Ashtankar; Nitin S. Ambatkar

In today’s CMOS VLSI era, power, speed and areas are the main issues of concern. Advances in microelectronic technology have led to more effective and secure communication and embedded intelligence in systems. In particular, to meet the increasing market demand for portable applications, these microelectronic devices consume very low power. Hence low power consumption becomes one of the most important criteria for the fabrication of recent DSP and high performance systems. It is the well known fact that the multipliers are the main power hungry elements of DSP and communication systems. If we can reduce the power consumption of the multiplier block, then we can reduce the power consumption of various digital signal processing chips and communication systems. This type of power efficient multipliers can be developed by reducing switching activities through architecture optimization. Reduction of switching activities through architecture optimization can be done using Bypassing Techniques (Turning of some columns or rows or both in the multiplier array whenever certain multiplier or multiplicand or both bits are zero). This paper presents various power efficient multiplier structures based on Bypassing Techniques. This will help in choosing among power efficient Bypass Multipliers for various portable DSP and communication systems.

Select Volume / Issues:

• Volume 3 Issue 2, Mar. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Switching Activity; Array Multiplier; Row and column Bypass Multiplier; Booth Recording Unit

Journal:

IJECCE

Volume:

3

Number:

2

Pages:

324-327

Month:

March