Parametric Optimization Speed, Power and Area for Carry Select Adder: A Survey

Akansha Rajoriya; Mr. Braj Bihari Soni

In today’s era the low power and faster adder logic is the major concern area in deep submicron technology. The addition speed is affected due to the time delay of carry signal propagated from one adder to its successive adder circuit. The addition of next two bits is generated only after the previous addition is completed and its carry is propagated for next bit addition. This speed limitation is trade off by the use of carry select addition by generating multiple number of carries and selecting the appropriate carry require for next addition bits. This carry selection is done by multiplexer logic. But this logic increases area of design. This paper discusses the area, power and delay efficient carry select adder (CSLA) design.

Select Volume / Issues:

• Volume 7,Issue 6, Nov. 2016

Year:

2016

Type of Publication:

Article

Keywords:

CSLA; RCA; CSKA

Journal:

IJECCE

Volume:

7

Number:

6

Pages:

354-357

Month:

November

ISSN:

2249-071X