CMOS Layout Design for Improved Latency Sequential Circuits

Sandeep Kumar Tiwari; Vinod Pathak

Microwind layout simulator is use to design the latches and flip flops and to calculates the parametric analysis such as power , switching delays, number of transistors, data and clock frequencies etc. The CMOS layouts are design and simulated for 8 bit asynchronous counter, 16 state mealy sequential circuit, 16 slot first in first out register for 8 bit data, and 4, 8 bit synchronize series connected XOR base CRC generator. The average power dissipation computed for these logic circuits are 22.29 μW, 32.66 μW, 78.12 μW, 60.27 μW and 120μW.

Select Volume / Issues:

• Volume 7,Issue 3, May 2016

Year:

2016

Type of Publication:

Article

Keywords:

TG; FSM; FIFO; Synchronization; CRC

Journal:

IJECCE

Volume:

7

Number:

3

Pages:

176-179

Month:

May

ISSN:

2249-071X