A Ring Oscillator Model and Design for a Self-biased CMOS PLL using Alpha-Power Law Based MOSFETs

Bhaskar Gopalan

A simple modified design procedure for a Maneatis cell based ring oscillator without any elaborate bias generator suitable to self-biased CMOS PLL using alpha-power law based MOSFETs is presented. Also presented is the time-domain mathematical model for the simulation of voltage-controlled oscillator (VCO). The design shows how to fix the operating biasing current for VCO through a simple circuit. A closed-form solution for the model shows good agreement between the SPICE simulated design and the model. The VCO is simulated for a 0.13um, 1.2v process and the designed result shows the tuning range of the VCO vary from 190MHz to 540MHz. The maximum % Total harmonic distortion (%THD) obtained is 2% and the maximum power dissipated by the ring oscillator is 672μW. Also the maximum variation in oscillation frequency arising from low-frequency supply voltage noise is 7%. The proposed design also is compared with Maneatis cell based ring oscillator with bias generator and shown that proposed design without any elaborate bias generator is better in terms of supply voltage noise effect and %THD but poorer in terms of tuning range.

Select Volume / Issues:

• Volume 6,Issue 3, May 2015

Year:

2015

Type of Publication:

Article

Keywords:

Self-Biased CMOS PLL; VCO; SPICE Models; Alpha-Power Law Mosfets; VCO Tuning Range; Total Harmonic Distortion THD; Power Dissipation And Supply Voltage Noise

Journal:

IJECCE

Volume:

6

Number:

3

Pages:

394-398

Month:

May