L}ow Power Architecture Design of De-Blocking Filter and Hardware Implementations in H.264/{AVC

Mrs. T. Priyadarsini; Mr. V. Thiyagarajan; Ms. R. Bharadhi

An adaptive in-loop de-blocking filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macro block (MB). In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standard defined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost.

Select Volume / Issues:

• Volume 5,Issue 6, Nov. 2014

Year:

2014

Type of Publication:

Article

Keywords:

De-Blocking Filter; H 264 AVC; Low Power Design; FPGA; Hardware Implementation

Journal:

IJECCE

Volume:

5

Number:

6

Pages:

1290-1296

Month:

November