A Novel High-Speed and Low-Energy 1-Bit Full Adder Cell Based on CNFET Technology

Nasibeh Rahmani; Yavar Safaei Mehrabani

Using both Capacitive Threshold Logic (CTL) and Transmission Gate Logic (TGL), a novel Full Adder cell based on 32nm Carbon Nanotube Field Effect Transistors (CNFETs) is presented in this paper. This approach leads to decrease both the delay and Power Delay Product (PDP) of the circuit. The proposed cell was compared with some 32nm CMOS and CNFET based classical and state-of-the-art designs. Comprehensive simulations with respect to variant supplies, operating frequencies, loads, and temperatures confirm the superiority of the proposed cell against its counterparts. Simulations show that the minimum PDP and delay belongs to the proposed cell.

Select Volume / Issues:

• Volume 5,Issue 6, Nov. 2014

Year:

2014

Type of Publication:

Article

Keywords:

CNFET; Full Adder Cell; Low Energy; Nanoelectronics

Journal:

IJECCE

Volume:

5

Number:

6

Pages:

1340-1345

Month:

November