Unavoidability Routine Enrichment for Real-Time Embedded Systems by Using Cache-Locking Technique

M. Shankar; Dr. M. Sridar; Dr. M. Rajani

In multitask, preemptive real-time systems, the use of cache memories make difficult the estimation of the response time of tasks, due to the dynamic, adaptive and non predictable behavior of cache memories. But many embedded and critical applications need the increase of performance provided by cache memories. Recent studies indicate that for application-specific embedded systems, static cache-locking helps determining the worst case execution time (WCET) and cache-related pre-emption delay. The determination of upper bounds on execution times, commonly called Worst-Case Execution Times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools and research prototypes

Select Volume / Issues:

• Volume 3 Issue 1, Jan. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Cache locking; real-time embedded system; Heptane; Miss Table; Multi-core architecture; Performance power ratio; Timing predictability

Journal:

IJECCE

Volume:

3

Number:

1

Pages:

41 - 45

Month:

January