Benchmarking Custom Artificial Neural Network Hardware Accelerator

Prof. S. R. Ganorkar; Padmaraj A. Jain

The goal of this work is to benchmark the custom design computational architecture supporting Artificial Neural Network (ANN) acceleration. The custom design optimizes the frequently used: multiply and accumulate (MAC) operations. In this work the performance of the custom design is compared with ARM and MIPS architectures supporting basic Single Instruction Multiple Data (SIMD) instructions. Benchmarking is performed by verifying the number of instructions required to compute n input neuron. The custom design is implemented using Very High Speed Integrated Circuits Hardware Description Language (VHDL) for Xilinx Spartan 6 Series FPGA Family. The execution speed is not considered as benchmarking parameter since the custom design is verified on the FPGA family. The ARM and MIPS architectures referenced here are basic architectures supporting SIMD instructions. Loading the inputs into registers and storing the results back into the memory depends upon the bus architecture supported and varies from architecture to architecture. Load and store instructions are not part of the benchmarking.

Select Volume / Issues:

• Volume 5,Issue 4, July 2014

Year:

2014

Type of Publication:

Article

Keywords:

ANN; MAC; RISC; SIMD; VHDL

Journal:

IJECCE

Volume:

5

Number:

4

Pages:

944-947

Month:

July