A Modified Hardware Efficient Watermarking Scheme for Intellectual Property Protection in Sequential Circuits

Jeebananda Panda; Siddhant Malik; Neeta Pandey; Asok Bhattacharyya

This paper presents a modified scheme for intellectual property protection in sequential circuits by embedding watermark in state transition graph in order to prove ownership in case of intellectual property theft. The hardware requirement, in general, increases for designs which are watermarked. The proposed scheme is hardware efficient than the existing scheme. The proposed scheme is illustrated through an example of a six bit sequence detector. The workability of the scheme is demonstrated by simulating RTL using VHDL simulators. The performance comparison with the existing scheme indicates that the proposed scheme is hardware efficient than the existing one.

Select Volume / Issues:

• Volume 5,Issue 4, July 2014

Year:

2014

Type of Publication:

Article

Keywords:

FSM; Intellectual Property Protection; VLSI; Watermark; Signature

Journal:

IJECCE

Volume:

5

Number:

4

Pages:

741-746

Month:

July