Subthreshold Leakage Minimization in MOSFET using Sleep Transistor Circuit

Shailesh Kumar Mukati; Tarun Verma; Dr. Rita Jain

The excessive power consumption has become one in all the first hindrances to the more advances of CMOS integrated circuits. Low power circuit style is a crucial analysis space. there are 3 primary stimuli for low power circuit design: setting friendly inexperienced computing, battery life extension for mobile applications, and rising self-sufficing battery replacement free applications like intelligent sensing element nodes. The leakage current in MOSFET is due to subthreshold leakage current due to parasitic pn junctions. The sleep transistor is use between CMOS logic and supply rail. Our technique, sleep transistor square measure placed between the circuits offer and provide rails to show off the run current flow throughout idle time this will be done by victimization one PMOS transistor and one NMOS transistor nonparallel with the transistors of every logic block to make a virtual ground and a virtual power supply. constant estimation victimization town simulation will acquire a comparatively correct estimation of the run distribution; but, this methodology needs an extended simulation time and is therefore computationally expensive.

Select Volume / Issues:

• Volume 5,Issue 3,May 2014

Year:

2014

Type of Publication:

Article

Keywords:

MOSFET; CMOS; Sleep Transistor Circuit

Journal:

IJECCE

Volume:

5

Number:

3

Pages:

571-575

Month:

May