Time-Cost Scheduler for Technological and Economic Challenges Related to Customized Cores and General Purpose Processors

Munesh Singh Chauhan

With the renewed interest in the customization of embedded processors for applications specific needs, it becomes imperative to understand its viability both economically and technologically thus avoiding pitfalls. Customization and scalability are two terms which are often used synonymously to denote add/ subtract of additional functional units or increase/ decrease of ports in memory register banks in processors. The advantage that comes out of customization is in the improved performance, reduced silicon area and power efficiency. With the option of parameterizing the inclusion/ exclusion of functional units the hardware can be made leaner and thus more energy efficient. Removal of redundant units results in shortening of critical path in circuits. Though the above advantages look significant but customization carries its own pitfalls which often are intractable. Firstly, it carries an immense overhead if performed in General Purpose Processors (GPUs). Changes in the hardware architecture results in code mismatch and thus necessitates ISA (Instruction Set Architecture) extensions or at times complete overhaul. Besides, users are often reluctant to adapt to the changes in ISA as it involves additional training. The final death knell may come from the limited commercial use of customized processor thus resulting in economic losses due to under-utilization of production units. Hence a new insight is needed that caters to the utilization of present technological advancements in processor customization but at the same time avoiding adverse economic fallout that comes from blindly forcing customization everywhere. A graded and selective use of customization in consonance with market and user needs is suggested. Therefore, predicting the development course of micro processors in general and embedded processors in particular will benefit businesses to correctly focus on the performance and efficiency of systems that use these processors.

Select Volume / Issues:

• Volume 5 Issue 1, Jan. 2014

Year:

2014

Type of Publication:

Article

Keywords:

Gartners Hype Cycle; Customized Core; Time-Cost Scheduler; Line Width; ISA; Moores Law

Journal:

IJECCE

Volume:

5

Number:

1

Pages:

1-7

Month:

January