H}ardware Implementation of {AES

Aakrati Chaturvedi; Preet Jain

The Advanced Encryption Standard algorithm can be efficiently programmed in software and implemented in hardware. Field Programmable Gate Array (FPGA) devices are considered as efficient and cost effective solution for hardware. This research is in context to efficient hardware implementation of AES algorithm with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language). This research is in context to efficient hardware implementation of AES algorithm with 128-192-256 key all in one module with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language). The software part has been created, processed and simulated through Xilinx ISE 9.2. A compact design approach has been chosen to implement the algorithm with minimal hardware. As for hardware, Spartan 3AN family device (XC3S700A) device is used.

Select Volume / Issues:

• Volume 5 Issue 1, Jan. 2014

Year:

2014

Type of Publication:

Article

Keywords:

AES; Affine; Array; Bit; Block; Byte; Cipher Key; Cipher text; Decryption; Key Schedule; Round Key; Rijndael; State; Word

Journal:

IJECCE

Volume:

5

Number:

1

Pages:

210-215

Month:

January