Design and Simulation of Pipelined FFT Processor Using FPGA

N. Amarnath Reddy; D. Srinivasa Rao

A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM). Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. A novel simple address mapping scheme and the modified radix 4 FFT also proposed. Finally, the pipelined 64-point FFT processor can be completely implemented within 20.093ns.

Select Volume / Issues:

• Volume 4 Issue 5, Sept. 2013

Year:

2013

Type of Publication:

Article

Keywords:

OFDM; FFT; DIF; Radix- 4; FPGA

Journal:

IJECCE

Volume:

4

Number:

5

Pages:

1361-1365

Month:

September