A Proposed FPGA Based Architecture for Generation of a Face Image

Santanu Halder; Abul Hasnat; Amina Khtaun; Debotosh Bhattacharjee; Mita Nasipuri

This paper aims to design a FPGA based architecture for generation of a new human face. This work is especially useful in criminal investigation department where a new face of a criminal is to be generated based on the description of eye-witness. Currently many image processing algorithms have been limited to software implementation which is slower due to the limited processor speed. So a dedicated processor for image processing algorithm is needed which was not possible until the advancement of VLSI technology. Now more complex system can be integrated on a single chip which provides a platform to process real time algorithm on hardware. This paper is an attempt to this direction. The FASY (FAce SYnthesis) System is a Face Database Retrieval and new Face generation System that is under development. One of its main features is the generation of the requested face when it is not found in the existing database. The new face generation system works in three steps – searching phase, assembling phase and tuning phase. In this paper the tuning phase using hardware description language and its implementation in a Field Programmable Gate Array (FPGA) device is presented.

Select Volume / Issues:

• Volume 4 Issue 3, May. 2013

Year:

2013

Type of Publication:

Article

Keywords:

Face Generation Architecture; Hardware Implementation; Pipelining; VHDL; FPGA

Journal:

IJECCE

Volume:

4

Number:

3

Pages:

871-877

Month:

May