Survey and Evaluation of D Flipflop for Low Power Counter Design Using Sub-Micron Technology

P. Brindha; A. SenthilKumar; V. P. Mohanapriyaa

As chip manufacturing technology is on the threshold of major evaluation, which shrinks chip size and performance, LFSR is implemented in layout level which develops low power consumption chip, using recent CMOS, sub-micrometer layout tool. This paper compares various architectures in terms of hardware implementation, power consumption, and CMOS layout using Microwind tool. Thus it provides a low power architecture implementation of LFSR counter using Microwind. The Microwind tool allows the designer to design and simulate an integrated circuit at physical description level.

Select Volume / Issues:

• Volume 4 Issue 2, March. 2013

Year:

2013

Type of Publication:

Article

Keywords:

LFSR Counter; Layout Generation; Physical Description; Pass Transistors; CMOS Topologies

Journal:

IJECCE

Volume:

4

Number:

2

Pages:

339-343

Month:

March