FPGA Implementation for Recduced Memory Using Scalable Encryption Algorithm

L. Malathi; L. J. Arthiha; R. Kanmani

Scalable encryption algorithm (SEA) is a parametric block cipher for resource constrained systems (e.g., sensor networks, RFIDs). It was initially designed as a low-cost encryption/authentication routine (i.e., with small code size and memory) targeted for processors with a limited instruction set (i.e., AND, OR, XOR gates, word rotation, and modular addition). Additionally and contrary to most recent block ciphers (e.g., the DES and AES Rijndael), the algorithm takes the plaintext, key, and the bus sizes as parameters and, therefore, can be straightforwardly adapted to various implementation contexts and/or security requirements.

Select Volume / Issues:

• Volume 4 Issue 2, March. 2013

Year:

2013

Type of Publication:

Article

Keywords:

AES; DES; FPGA; SEA

Journal:

IJECCE

Volume:

4

Number:

2

Pages:

668-670

Month:

March