Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

Eshwararao. Boddepalli

This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating one matrix line. Both fully combinational and pipelined versions of the algorithm were designed and tested until a functional physical implementation was obtained, including a user interface. The paper also presents new way to implement hardware structures inside programmable circuits, using portable schematic design from “Altium Designer” software environment instead textual description with HDL languages

Select Volume / Issues:

• Volume 2 Issue 2, Oct. 2011

Year:

2011

Type of Publication:

Article

Keywords:

FPGA; parallel matrix structure; non-restoring division algorithm; schematic design

Journal:

IJECCE

Volume:

2

Number:

2

Pages:

155-161

Month:

October