Efficient Hybrid VLSI Architecture Using Hadamard Transform

Nitesh Dodkey; Prof. Divya Jain; Prof. Vikas Gupta

Fully-pipelined and parallel modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N = 4. It is shown further that the HT of transform-length N = 8 can be obtained from two 4-point HT modules, and similarly, the HT of transform-length N=16 can be obtained from four 4-point HT modules. Long-length transforms may, however, be computed from these short-length modules as N-point transforms can be computed from 2M number of M point HT-modules, where M = N1/2. The proposed architectures are coded in VHDL, simulated by Xilinx ISE tool for validation and testing; and synthesized thereafter to be implemented in FPGA device Virtex-E. From the synthesis result, it is found that the pro-posed designs involve considerably less number of slices.

Select Volume / Issues:

• Volume 4 Issue 2, March. 2013

Year:

2013

Type of Publication:

Article

Keywords:

Hadamard Transform; Parallel Processing; Pipelining; FPGA; DOT

Journal:

IJECCE

Volume:

4

Number:

2

Pages:

577-580

Month:

March