Design of 16-Bit Carry Select Adder with Low Power 8-Transistor Full Adder Cell

Ravichandra. B; V. Rama Dinesh Kumar; SK. Rehana Tabassum; M. Balakrishna Yadav; S. Sai Rakesh

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) chips such as application-specific digital signal processing (DSP) and microprocessors chips. An adder determines the overall performance of the circuits in most of those systems. Carry select adder (CSLA) is one of the fastest adders used in many data processing processors to perform fast arithmetic functions of n-bit additions when compared with ripple carry adders. From the structure of the CSLA, it is clear that there is a scope for reducing the area and power consumption in the CSLA.This work uses simple and efficient transistor level modifications to significantly reduce the area and power of the CSLA.Based on these modifications in this paper 16-bit CSLA architecture have been developed and compared with the regular CSLA architecture. The proposed design has reduced area and power as compared with the regular CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular CSLA.

Select Volume / Issues:

• Volume 4 Issue 2, March. 2013

Year:

2013

Type of Publication:

Article

Keywords:

CSLA; Full Adder; Multiplexer; Very Large Scale Integration VLSI

Journal:

IJECCE

Volume:

4

Number:

2

Pages:

451-454

Month:

March