Design, Implementation and Performance Analysis of 4-bit Full Ripple Carry Adder Using Adibatic Logic in 45nm CMOS Sub-micron Technology

Jitendra R. Patel; Prof. Sandip Nemade; Prof. Vikas Gupta

In this paper I had implemented the different three types of 4-bit adder using adiabatic logic and conventional CMOS logic in 45nm technology with LT spice. As we know Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. we have compared all three techniques conventional CMOS, 1n-1p Quasi and 1n-1p split level logic in 1-bit as well as 4-bit adder for power dissipation and as result suggest adiabatic method has low power dissipation compared to conventional CMOS. We got minimum power dissipation and energy consumption in 1n-1p split adiabatic logic.

Select Volume / Issues:

• Volume 4 Issue 1, Jan. 2013

Year:

2013

Type of Publication:

Article

Keywords:

Adibatic Logic; DSP; CMOS; Low Power

Journal:

IJECCE

Volume:

4

Number:

1

Pages:

7-11

Month:

January