Optimised ASIC Ready FPGA Design

Prof Sandip Nemade; Mr Mohd Ahmed

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and weaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This paper investigates as how to optimize a design for an FPGA and what steps should be taken in the design to enable seamless porting from FPGA to ASICS for volume production

Select Volume / Issues:

• Volume 1 Issue 1, April 2011

Year:

2011

Type of Publication:

Article

Keywords:

Optimised FPGA vs ASICS; FPGA to ASIC Porting

Journal:

IJECCE

Volume:

1

Number:

1

Pages:

35-40

Month:

April