A 1V Phase Frequency Detector (PFD) with 180nm CMOS Technology

N. K. Kaphungkui

In this paper, designing of a Phase frequency detector with 180nm CMOS technology is presented. The main objective of the designed circuit is to reduce the power dissipation with a low voltage supply of 1V. Phase frequency detector has a wide range of applications but one of the main application is in modern day phased locked loop, it serve as a main building block. PFD (Phase Frequency Detector) is a circuit that measures the phase and frequency difference between two signals, and has two outputs UP and DOWN which are signalled according to the phase and frequency difference of the two input signals. The designed circuit shows a satisfactory result with the low supply voltage. The detection of phase difference occurs only at the rising edge of the two clock signal. The total power dissipation from the circuit is only 3.88uW which is considerably low. In the field of IC design power dissipation of the circuit is always an important factor. The lower the power dissipation the longer the service time of the battery powered electronics circuit.

Select Volume / Issues:

• Volume 4 Issue 1, Jan. 2013

Year:

2013

Type of Publication:

Article

Keywords:

Phase Locked Loop; Phase Frequency Detector; Phase Error; VCO

Journal:

IJECCE

Volume:

4

Number:

1

Pages:

48-50

Month:

January