Virtex 4 Field Programmable Gate Array Based 32 bit FPM

Pardeep Sharma; Gurpreet Singh; Hartej Singh Saini

FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. We present FPGA floating-point multiplication. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogramability and parallelism of the FPGA device but also require a general purpose multiplier unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 32-bit Single precision circuits that also provide rounding and exception handling. We introduce an algorithm for multiplication and analyze its performance on Virtex 4 having device (XC4VLX15-SF363) hardware module at speed grade -12.

Select Volume / Issues:

• Volume 3 Issue 6, Nov. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Floating point Multiplier; FPGAs; Xilinx and Virtex 4

Journal:

IJECCE

Volume:

3

Number:

6

Pages:

1550-1554

Month:

November