High Speed Bit-Parallel Systolic Multiplier over GF (2m) for Cryptographic Application

S. Arul Mozhi; Beena Thomas

A bit parallel systolic multiplier in the finite field GF(2m) over the polynomial basis where irreducible polynomial generate the field GF(2m) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed with other existing multipliers. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular, and therefore, well-suited for VLSI implementation with fault tolerant design.

Select Volume / Issues:

• Volume 3 Issue 6, Nov. 2012

Year:

2012

Type of Publication:

Article

Keywords:

AOP; Cryptography; Galois Field; Systolic Architecture

Journal:

IJECCE

Volume:

3

Number:

6

Pages:

1601-1604

Month:

November