Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM Encryption and Decryption

P. Ajay Kumar; A. Krishna Kumari

The Advanced Encryption Standard (AES) is a symmetric key algorithm and its recently standardized authentication Galois/Counter Mode (GCM) have been utilized in various security-constrained applications. Many of the AES-GCM applications are power and resources constrained and require efficient hardware implementations. In this paper, different application-specific integrated circuit (ASIC) architectures of building blocks of the AES-GCM algorithms are evaluated and optimized to identify the high-performance and low-power architectures for the AES-GCM. The implementation of GHASH operation requires 11-clock cycles for 128-block, and is pipelined with AES 12/14/16 clock cycles for 128/192/256-bits. It has high throughput and less hardware architecture.

Select Volume / Issues:

• Volume 3 Issue 6, Nov. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Advanced Encryption Standard; Galois Counter Mode; High Performance; Low Power

Journal:

IJECCE

Volume:

3

Number:

6

Pages:

1605-1607

Month:

November