An Efficient System On-Chip Bus with OCP Interface

Jessi Mallika D.; Mrs. A. Krishna Kumari

The implementation of a huge scale SoC (System-on-chip) is becoming difficult task not only due to its complexity, but also the design of a more amount of IPs. A consensus interface protocol for IP cores is becoming significant and even predictable for a successful SoC establishment. Open Core Protocol (OCP), with its candidness, concerted, not-for-profit nature, and inherent large industry member base, is quickly becoming a feasible and preferable solution over a close or an in-house standard. In this paper a well-defined interface standard, the Open Core Protocol (OCP), has adopted to design the internal bus architecture. An efficient bus architecture to support most advanced bus functionalities defined in OCP has been developed. These functionalities include burst transactions, lock transactions, pipelined transactions, and out-of-order transactions. First model and design the on-chip bus with transaction level modeling for the consideration of design flexibility and fast simulation speed. Then implement the RTL (Register Transfer Level) models of the bus for synthesis and gate-level simulation. Experimental results show that the proposed TLM (Transaction Level Modeling) model is quite efficient for the whole system simulation and the real implementation can significantly save the communication time.

Select Volume / Issues:

• Volume 3 Issue 6, Nov. 2012

Year:

2012

Type of Publication:

Article

Keywords:

AMBA; AXI; FSM; OCP; SoC

Journal:

IJECCE

Volume:

3

Number:

6

Pages:

1513-1518

Month:

November