H}igh Speed Symmetric Transparent BIST on {FPGA

Srikanth Lammatha; Prof. A. S. Srinivasa Rao; E. Jaya

Symmetric Transparent BIST has been proposed as a means to skip the signature prediction phase during RAM testing thereby testing time can be reduced. The proposed symmetric transparent BIST scheme is for single bit and multiple bit (word) RAM’s. The principle of this is a characteristic of a polynomial is modified based on the application of sequence of March events. In this paper an FSM is used to generate the mach events and are applied for the RAM to verify it. Compared to previous BIST techniques, controller complexity is reduced. Due to the reduction in the controller complexity the hardware required for the BIST also reduces and thereby reducing the power and delay.

Select Volume / Issues:

• Volume 3 Issue 5, Sept. 2012

Year:

2012

Type of Publication:

Article

Keywords:

Built in self test; design for testability; integrated circuit reliability; Self testing; RAM testing

Journal:

IJECCE

Volume:

3

Number:

5

Pages:

1286-1289

Month:

Sept.