Power Optimization on Functional Units of a Generic Data-path Subsystem

Bantupalli Divakar; K V Lalitha Bhavani

Data path is the core of the processor, where all computations are performed. The other blocks in the processor are support units. At present, most of the popular processor hardware synthesis tools give higher priority to delay. So the processor synthesis tools tend to generate data path architecture for faster implementation. With increasing importance of power reduction on a processor, it is becoming necessary to evaluate different data path architectures from the point of view of both delay and power. This work is aimed at characterizing various architectures implementations of common operators for power, delay and area for different algorithms of adders, multipliers, comparators, shifters etc. and selecting a particular low power architecture where delay is not critical. Finally optimizing the data paths for a general purpose processor. Most of power consumption in the processor is due to adders, multipliers, shifters and comparators.

Select Volume / Issues:

• Volume 3 Issue 4, July 2012

Year:

2012

Type of Publication:

Article

Keywords:

Bypass multipliers; tree multipliers; mixed style multipliers; clock gating

Journal:

IJECCE

Volume:

3

Number:

4

Pages:

834-838

Month:

July