Design and Implementation of Standby Leakage Power Reduction Technique for Nano scale CMOS VLSI Systems

P. Srinivasulu.; R. V. Kiran kumar; Dr. K. Srinivasarao; Dr. A. Vinaya Babu

In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (ISUB) and the band-to-band tunneling (BTBT) current (IBTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25 ◦C to 100 ◦C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25 ◦C and 100 ◦C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.

Select Volume / Issues:

• Volume 3 Issue 4, July 2012

Year:

2012

Type of Publication:

Article

Keywords:

Band to band tunneling leakage; gate leakage; leakage current; leakage power; optimal body bias voltage; subthreshold leakage

Journal:

IJECCE

Volume:

3

Number:

4

Pages:

857-864

Month:

July