Designing & Simulation of 8-Bit MIPS RISC Processor

Akhilesh Singh Thakur; Dr. Ravi Shankar Mishra; Prof. Puran Gaur

This paper targets the implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor via VHDL (Very high speed integrated circuit Hardware Description Language) design. The goal of this paper is to enhance the simulator based approach by integrating some hardware design {&} simulating them in pipelined (3 level) {&} non-pipelined modes so as to assess the performance of the processor in each of the modes.

Select Volume / Issues:

• Volume 2 Issue 1, Sep 2011

Year:

2011

Type of Publication:

Article

Keywords:

MIPS; RISC; PIPELINING; VHDL

Journal:

IJECCE

Volume:

2

Number:

1

Pages:

27-29

Month:

Sept