A New Implementation of CMOS Full-Adders for Energy-Efficient Arithmetic Applications

S. Madhava Rao; Prof. K. Amarnath; V. Santhisri

We present two high-speed and low-power fulladder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18- m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the fulladder inputs, besides the current provided from the powersupply. Post-layout simulations show that the proposed fulladders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

Select Volume / Issues:

• Volume 3 Issue 3, May 2012

Year:

2012

Type of Publication:

Article

Keywords:

Arithmetic; full-adder; high-speed; lowpower

Journal:

IJECCE

Volume:

3

Number:

3

Pages:

682-686

Month:

June