Reducing Power and Leakage in CMOS Logic with Sleep and Stack Transistor Technique

Manish Kumar Chandela; Laxmi Narayan Gahalod

The major design constraint for VLSI circuits and systems is the reduce power dissipation. The power dissipation in VLSI circuits depends on the switching activity, supply voltage and output load capacitance. The leakage power dissipation cause by parasitic pn junctions and subthreshold leakage is a component of static power dissipation in CMOS circuits. It is because of the generation of leakage currents in the MOS transistors. The various methodologies such as series connected stack transistors, sleep transistor, sleepy keeper transistors techniques. These techniques reduces the static power with a moderate area overhead as compare to CMOS circuit design...

Select Volume / Issues:

• Volume 8, Issue 4, July 2017

Year:

2017

Type of Publication:

Article

Keywords:

Stack Transistor; Sleep Transistor; Precharge Evaluate

Journal:

IJECCE

Volume:

8

Number:

4

Pages:

226-229

Month:

July

ISSN:

2249-071X