Reduction of Static Power Leakage in CMOS VLSI Circuits

Shailesh M. Keshkamat

As CMOS IC Technology is scaled down to lesser dimensions low power becomes a significant parameter of consideration in system design due to Static Power Dissipation occurring in standby mode. This paper reports the design and implementation of logic circuits for reduction of leakage power in device with channel length scaling to sub-100nm. A circuit technique to mitigate the leakage currents in MOSFET through controlling the voltage at the source terminal is implemented and the power dissipation results are compared with that for conventional technique. This has been carried out on the universal gates for the design of combinational and sequential circuits. Improvements in the power dissipation have been observed through the simulation results obtained using Cadence Virtuoso at 45nm technology

Select Volume / Issues:

• Volume 8, Issue 4, July 2017

Year:

2017

Type of Publication:

Article

Keywords:

Static Power Dissipation; Sub-100 Nm; Source Terminal; Universal Gates

Journal:

IJECCE

Volume:

8

Number:

4

Pages:

223-225

Month:

July

ISSN:

2249-071X