Optimization of FPGA Architecture for Uniform Random Number Generator using LUT-SR Family

Ms. Rita Rawate; Prof. M. V. Vyawahare

Field-Programmable Gate Arrays (FPGAs) are widely used to implement logic without going through an expensive fabrication process. Field-programmable gate array optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. The software community has developed a number of high-quality, long period Random Number Generators (RNGs), some of which have been adapted for use in FPGAs. However, these generators were designed to meet the needs of word-level instruction processors, and so are less efficient when mapped to the bit-level operations available in FPGAs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise XOR operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resource–quality balance compared to previous FPGA-optimized generators. This paper deals with optimization of FPGA and simulations is done in VHDL.

Select Volume / Issues:

• Volume 6,Issue 6, Nov. 2015

Year:

2015

Type of Publication:

Article

Keywords:

FPGA Field Programming Gate Array; LUT Look UP TABLE; LUT-SR Look Up Table Shift Register; Uniform Random Number Generator RNG

Journal:

IJECCE

Volume:

6

Number:

6

Pages:

756-761

Month:

November