Design and Implementation of CSR for DDR4 Memory Controller

Mr. Sathish D.; Dr. PA Vijaya; Mr. Ramudu B

This paper deals with the design and implementation of Control Status Register (CSR) for DDR4 memory controller and also presents proposed architecture of the DDR4 memory controller along with brief details of individual blocks. Control register stores different timing parameters to generate different timing delays for various commands for DDR4 memory like refresh, self refresh, power down entry and exit, read and write operations, On-Die Termination, different modes of operation and also updates the status register when read from or written into registers. The timing parameters are written by the APB (Advanced Peripheral Bus) master and CSR receives this information through APB slave interface which is at the controller side and stores this information in respective registers of CSR. DDR4 core part of memory controller has timing and command generator unit which reads the timing parameters from the CSR and generates timing delays for each memory related commands for DDR4 memory for proper operation and also updates Status Register on each read or write success/failure. The entire design was coded in System Verilog hardware description language and simulated using ModelSim 10.1C version. The results of various operations were verified using different test cases.

Select Volume / Issues:

• Volume 6,Issue 3, May 2015

Year:

2015

Type of Publication:

Article

Keywords:

Memory Controller; CSR; DDR4; Digital Circuits; APB Protocol; SDRAM

Journal:

IJECCE

Volume:

6

Number:

3

Pages:

335-340

Month:

May