HDL Design for 1 Zetta Bits Per Second (1 Zbps) Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card Design for 6th Sense and Future Ultra High Wireless and Mobile Communication Protocol Cards

P. N. V. M SASTRY; D. N. Rao; S. Vathsal

The Aim is to HDL Design & Implementation for Exa Bit Rate Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card for Ultra High Speed Wireless Communication Products like Network On Chip Routers, Data Bus Communication Interface Applications, Cloud Computing Networks , Zetta bit Ethernet at Zetta Bit Rate Of Data Transfer Speed. Basically This Serializer Array Converts 64 bit parallel Data Array in to Serial Array Form on Transmitter Side and Transmission Done through High Speed Wireless Serial Communication Link and also Converts this Same Serial Array Data into Parallel Data Array on the Receiver Side by De-Serializer Array ASIC without any noise, also measure Very High Compressed Jitter Tolerance & Eye Diagram, Bit Error Rate through Analyzer. This LVDS Data SER-De-SER mainly used in High Speed Bus Communication Protocol Transceivers, Interface FPGA Add On Cards. The Process Of Design is Implemented through Verilog HDL / VHDL, Programming & Debugging Done Latest FPGA Board.

Select Volume / Issues:

• Volume 6 Issue 1, Jan. 2015

Year:

2015

Type of Publication:

Article

Keywords:

LVDS; SER; ASIC; NOC

Journal:

IJECCE

Volume:

6

Number:

1

Pages:

9-13

Month:

Jan.-Feb.

ISSN:

2249-071X