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H}ardware Implementation of Neural Network Using {VHDL

Anand Pratap Singh; Girraj Prasad Rathor
The purpose of this paper is to present the state of the art in neural network hardware architectures and provide a broad view of principles and practice of hardware implementation of neural networks. The investigation of neuron structures is an incredibly difficult and complex task that yields relatively low rewards in terms of information from biological forms (either animals or tissue). The structures and connectivity of even the simplest invertebrates are almost impossible to establish with standard laboratory techniques, and even when this is possible it is generally time consuming, complex and expensive. Recent work has shown how a simplified behavioural approach to modelling neurons can allow “virtual” experiments to be carried out that map the behaviour of a simulated structure onto a hypothetical biological one, with correlation of behaviour rather than underlying connectivity. The problems with such approaches are numerous. The first is the difficulty of simulating realistic aggregates efficiently, the second is making sense of the results and finally, it would be helpful to have an implementation that could be synthesised to hardware for acceleration. In this paper we present a VHDL implementation of Neuron models that allow large aggregates to be simulated.
Select Volume / Issues:
Year:
2012
Type of Publication:
Article
Keywords:
Neural Network; VHDL; Classifications; NN; ASIC; FPGA
Journal:
IJECCE
Volume:
3
Number:
4
Pages:
1007-1015
Month:
July
Hits: 1243

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