Data Access Time Reduction for 3D Data Bus in Mixed Cases of Embedded Bus Switches and Inserted Signal Repeaters

Chia-Chun Tsai

Data are frequently running on the 3D data bus of a stacked-layer chip at different timing periods, their data access time dominates the chip performance. In this paper, we proposed an integrated algorithm that combines a few methodologies for data access time reduction. The first strategy is to embed bus switches into data bus to isolate those unnecessary across local bus capacitive loadings accessed at different timing periods. Their critical access time and average access time can be obviously reduced. Moreover, two other strategies, sizing all the source drivers and inserting repeaters into bus wires, can reduce their access time in advance to a given 3D data bus with embedded bus switches. The integrate algorithm can work with an independent strategy or any mixed cases of combining different strategies for minimize their access time. Experimental results show their comparison. The critical access time and average access time of a 3D data bus with embedded bus switches are reduced up to 54.56% and 60.53%, respectively, on average. For the case of inserting repeaters into bus wires to a given data bus with embedded bus switches, the reduced rate of critical access time and average access time are 77.99% and 68.15%, respectively, in running time of 0.747 seconds and repeater sizes of 107 on average.

Select Volume / Issues:

• Volume 10,Issue 3, May 2019

Year:

2019

Type of Publication:

Article

Keywords:

3D Data Bus; Data Access Time; TSV; Bus Switch; Signal Repeater

Journal:

IJECCE

Volume:

10

Number:

3

Pages:

127-140

Month:

May

ISSN:

2249-071X