Area & Power Efficient Non Overlapped Clock Pulse Shift Register Design

Md. Ajaz Ahmad; Nikhil Ranjan; Manish Jain

This paper discusses the design of 256 latch base shift register with area and power optimization synchronized with pulse clocking scheme...

Select Volume / Issues:

• Volume 8, Issue 4, July 2017

Year:

2017

Type of Publication:

Article

Keywords:

Pulse Clock; Latch

Journal:

IJECCE

Volume:

8

Number:

4

Pages:

263-267

Month:

July

ISSN:

2249-071X