Power and Delay Improvement of Edge Triggered Flip Flop Design Using Transmission Gate

Rachit Pawar; Ashish Raghuwanshi

The most of the area in sequential digital integrated circuits is consume by flip flops and most of the power is dissipates due to the dynamic power dissipation by voltage transition at internal nodes of circuit when both input and output node is at the same state. In related work, many power dissipation minimization techniques are use which may cause increase in number of transistors for design. This paper discusses the schematic and CMOS layout design and its timing simulation of edge triggered flip flop with cross connected NAND Logic design by transmission gates. The use of transmission gate exhibits area and power optimized design as the transmission gate (TG) reduces number of stray capacitance and less number of transistors

Select Volume / Issues:

• Volume 8,Issue 2, Mar. 2017

Year:

2017

Type of Publication:

Article

Keywords:

Flip-Flop; TG; Hold Time; Latch; Performance; Improvement; Process Variations; Setup Time

Journal:

IJECCE

Volume:

8

Number:

2

Pages:

109-112

Month:

March

ISSN:

2249-071X