Transmission Gate Base Adder Area Optimization in Power-Constrained Environments

Abhishek Chourasia; Prof. Umashankar Kurmi

In this work a floating point (FP) adder is design with reduce area and low power pass transistor dynamic logic is proposed. The design logic has been design using 50 nm technology on Microwind layout simulator. Compared to a conventional adder with this architecture, the proposed unified architecture can reduce the hardware resources. The two 4 bit FP adder are pipelined to for 8 bi FP adder . The limitation of carry propagation in parallel adder with speed trade off is overcome with this architecture. The layout design by dynamic CMOS logic optimizes the area in term of number of transistors with the comparison of conventional adder logic.

Select Volume / Issues:

• Volume 7,Issue 6, Nov. 2016

Year:

2016

Type of Publication:

Article

Keywords:

FP; Area; Speed; Power; Transmission Gate

Journal:

IJECCE

Volume:

7

Number:

6

Pages:

345-348

Month:

November

ISSN:

2249-071X