Parametric Optimization of Pulse Latch Shift Register in Deep Submicron Technology

Shivani Tomar; Vishal Rajauriya

This paper is base on power and area optimization of shift register which is synchronized with pulse clock. The register is design with pulse clock base latches, this reduces the area of design. The pulse clock generator is design and connected to the group of the latches in several sub shifter registers to increase the data length. The design will implemented on 0.05um technology using MICROWIND layout editor tool.

Select Volume / Issues:

• Volume 8,Issue 1, Jan. 2017

Year:

2017

Type of Publication:

Article

Keywords:

Pulse Latch; Shift Register; Level Triggered

Journal:

IJECCE

Volume:

8

Number:

1

Pages:

29-31

Month:

January

ISSN:

2249-071X