R}outer Architecture for Network on Chip Using {FPGA

P. B. Domkondwar; D. S. Chaudhari

On Single chip integration of storage and computational block has becoming feasible due to continuous shrinkage of CMOS technology [1]. Field programmable gate arrays (FPGA’s) are power efficient devices [3] support more complex design with good performance and low cost [6]. For effective global on-chip communication, on-chip routers provide essential routing functionality with low complexity and relatively high performance [1]. Routers implemented within FPGA can give better performance with reduced area and hence reduced power consumption [4]. This paper will provide an overview of related work for on-chip router architectures.

Select Volume / Issues:

• Volume 3 Issue 2, Mar. 2012

Year:

2012

Type of Publication:

Article

Keywords:

FPGA; NOC Router; Round-Robin Arbiter; First In First Out Buffer; Finite Sate Machine

Journal:

IJECCE

Volume:

3

Number:

2

Pages:

289-291

Month:

March