Analysis and Design of Low-Energy Flip-flops in a Deep Submicron Bulk CMOS Process

Priyanka Dhoke; Akhilesh Jain

In this paper a leakage and dynamic power optimized and area efficient flip flop is design in VLSI circuits. The flip-flops have been designed on CMOS layout editor in a low-power 50-nm bulk technology. In applications where energy efficiency is prioritized prior to operating frequency, the proposed FF topology may be well suited for implementation.

Select Volume / Issues:

• Volume 7,Issue 6, Nov. 2016

Year:

2016

Type of Publication:

Article

Keywords:

CMOS; TG; SEU; DFF; TFF; JKFF

Journal:

IJECCE

Volume:

7

Number:

6

Pages:

313-316

Month:

November

ISSN:

2249-071X