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Design of Duail Rail Adiabatic Energy Recovery Logic

Riju Nema; Ruby Awasthi
This work is base on adiabatic power dissipation technique for dynamic power dissipation reduction using deep submicron i.e., 50nm CMOS technology. The timing simulation and power dissipation analysis is done on MICROWIND layout simulator tool. The comparative analysis with related work shows that the area require for design at 90nm technology is reduce up to 63% and the power dissipation is reduce up to 93.4%. That of for 50nm technology, area is reduce up to 52% and power up to 96.8%. Adiabatic switching method is use to suppress the dynamic power dissipation in CMOS circuits. This power dissipation is mainly cause during the time of output capacitive load charging and discharging time i.e., during the rise and fall time. The adiabatic technique uses the charge recovery concept. The current flow from supply voltage either Vdd or ground to output load capacitor is controlled in a way that the energy dissipation during the rise time or fall time and output load capacitor dissipation is reduced.
Select Volume / Issues:
Year:
2016
Type of Publication:
Article
Keywords:
Adiabatic; Single Rail; Dual Rail Supply; Dynamic Power; CMOS
Journal:
IJECCE
Volume:
7
Number:
3
Pages:
180-183
Month:
May
ISSN:
2249-071X
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