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Area & Power Efficient Non Overlapped Clock Pulse Shift Register Design

Md. Ajaz Ahmad; Nikhil Ranjan; Manish Jain
This paper discusses the design of 256 latch base shift register with area and power optimization synchronized with pulse clocking scheme...
Select Volume / Issues:
Year:
2017
Type of Publication:
Article
Keywords:
Pulse Clock; Latch
Journal:
IJECCE
Volume:
8
Number:
4
Pages:
263-267
Month:
July
ISSN:
2249-071X
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