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Power Optimization using Current Mode Pulse Flip Flop

Rahul Yadav (M. Tech Scholar); Rahul Shrivastava; Vijay Yadav
The conventional synchronization clocks signals are becoming increasingly difficult for multiple higher frequency integrated circuits because skew, jitter, and variability are often proportional to large latencies. A current-mode pulsed flip-flop with enable (CMPFFE) is design with optimize power dissipation which uses current for clocking instead of voltage. It designs with input current-comparator (CC) stage, a register stage, and a static storage cell. The CC stage compares the input push pull current with a reference current and conditionally amplifies the clock to a full-swing voltage pulse that triggers the data to latch at the register stage. This flip flop is design using 50 nm technology having the channel length of 0.005 nm and channel width of 0.015 nm size
Select Volume / Issues:
Year:
2017
Type of Publication:
Article
Keywords:
Power Optimization; Flip Flop; Cmpffe; Current Comparator; Latencies
Journal:
IJECCE
Volume:
8
Number:
4
Pages:
251-252
Month:
July
ISSN:
2249-071X
Hits: 160

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